Bidirectional decade counter



Sept. 29, 1964 R. A. LElGH'rNER BIDIRECTIONAL DECADE COUNTER Filed Deo. 28, 1959 who@ E INVENTR. ROBERT A. LE|GHTNER M @/u'aemya United States Patent O 3,151,252 BiDiiiECTiN/AL DEQADE CUNTER Robert A. Leightner, Tioga Center, NSY., assigner to international Business Machines Corporation, New Yorh, NX., a corp ration of New Yorh Filed Dee. 28, 1959, Ser. No. 362,341 9 Claims. (Cl. Shi-$8.5)

This invention relates to a counting device and more particularly to a decade counting device capable of bidirectional counting operations.

Counters may be defined generally as devices capable of changing from one to the next of a sequence of distinguishable states upon each receipt of a discreet input signal. Certain bidirectional counters employ a plurality of stages of bistable devices, such as flip-hops, each stage of which includes a plurality of gates. Each of these gates is arranged to be conditioned by the flip-flop in its stage to provide a carry signal, or pass an input pulse, to the next succeeding stage. In certain bidirectional count* ers, the iiip-op of one stage is fed from the flipdlop of the preceding stage thereby resulting in a cumulative time delay. In other bidirectional counters, the input pulses are applied to each stage and two or more gates are employed in each stage to gate the input pulses.

Counters find extensive uses in a variety of computing applications. It is desirable that such counters operate at rates as high as possible. lt is also desirable to construct such counters from a minimum number of standard components to achieve standardization and minimize construction cost,

In accordance with the present invention, a bidirectional counter is provided which includes a plurality of substantially identical stages. Each of these stages includes a bistable device, such as a flip-flop. Certain of the stages include a single gate which is conditioned by the ip-op of that stage to pass, or block, an input signal to the iip-op of the next succeeding stage. An AND (negative AND) gate is connected to the last two flipops of the counter. Upon the occurrence of a particular count in the counter, the AND gate conditions a complement gate to trigger certain of the lip-tlops upon the reception of the next input pulse. Input pulses cause the binary states of the 'flip-flops of 'the counter to advance from through 4 and then ll through 15 when adding which represents a decimal count of input pulses through 9. When the counter is subtracting, the binary states of the flip-flops decrease from through l1 and Vthen 4 through 0. The particular scheme of counting employed greatly reduces the total number of components required.

Another feature of the present invention resides in the particular gating arrangement which results in a negligible current requirement in the control input of the gate thereby allowing a high impedance to be used between the gate control terminal and the ilip-lop output. The use of such a high impedance prevents the counter from changing its accumulated total when it is switched from the add mode to the subtract mode.

A further feature of the present invention is in the provision of a bidirectional counter employing bistable devices all of which are fed input pulses. This arrangement removes the successive amplications of noise and cumulative time delays present in similar counters employing caseaded Hip-flops.

Another feature of the present invention is in the provision of a counter employing a plurality of transistorized hip-Hops which are reset to a predetermined state by opening a ground connection to one of the transistors of each of the flip-hops. This arrangement results in a savings of a number of components over prior transistor counters.

These and other features of this invention may be more fully appreciated when considered in light of the following specification and lthe single figure of the drawing which illustrates a bidirectional decade counter in accordance with the principles of the instant invention.

Referring to the drawing, a four stage bidirectional decade counter is shown in block diagram form. The iiip-ilops and the inhibit gates employed in each stage of the counter are substantially identical, and a description of one stage should sul-lice for an understanding of the construction of the remaining stages. A detailed circuit diagram of the flip-flop and the gate of only the first stage is illustrated.

The bidirectional decade counter illustrated in the drawing is comprised of four stages deined by a ilip-op 1t) and an inhibit gate 18, a flip-hop Ztl and an inhibit gate 28, a dip-flop 30 and an inhibit gate 38, and flip-dop 40. Each of the stages of the counter also includes an add-subtract mode switch 16, 26, 36 and 46. These mode switches are arranged so that they operate together. Although a mechanical type mode switch is illustrated, i't is to be understood that other types of switches, such as electronic switches, may be employed. An electronic switch is preferred for use as the mode switch, but a mechanical type switch is shown for simplicity of illustration.

The inhibit gates 18, 28 and 38 are connected in series with the input pulse source. Each of these gates is conditioned by the state of its associated dip-Hop, 10, 20 and 3l), respectively, to pass or block input pulses as Will be explained in greater detail hereinafter. The input pulses are applied to an input terminal 11 of the flip-flop 16 and to the series circuit including the inhibit gates 18, 28 and 38. When an input pulse passes through the inhibit gate 18, it is applied to the inhibit gate 28 and an input terminal 21 of the iiip-op 2t). When a pulse is passed by the inhibit gate 28, it goes to the inhibit gate 38 and an input terminal 31 of the flip-flop 30. A pulse passed by the inhibit gate 3% is applied to an input terminal 41 of the Hip-flop 40. The input terminals 11, 21, 31 and 41 of the dip-flops 19, 2u, 30 and 40, respectively, are trigger or complement inputs. Therefore, when. a pulse is applied "to any of these inputs, the associated flipdiop is caused to change state, i.e., from the One to the Zero state or vice versa.

According to a feature of this invention, a complement gate 6h, which is an inhibit circuit, is employed to complement the ip-iiops 2t), 30 and 40 during particular phases of the operation of the bidirectional counter. The complement gate 6d is conditioned by the output from an AND (negative AND) gate 50 to pass an input pulse to complement 'the dip-flops 2i), 30 and 4G. The AND gate 5@ conditions the complement gate 60 whenever like signals are applied to input terminals 52 and 54 from the ip-iiops 31) and 40, respectively. The complement gate @il and the gate 50 are not illustrated in detail because such devices are well known in the art. They may take numerous forms, and for example, they may be diode type gates. An output signal is produced from the AND gate 5@ when both of its input terminals are at ground potential which output signal conditions the complement gate 60 to pass a postive input pulse. Diodes 70 and 80 are connected between the complement gate 60 and the flip-hops 20 and 30, respectively. These diodes are arranged to block the passage therethrough of pulses from the inhibit gates 18 and 2S.

The nip-flop employs a pair of transistors 100 and 102 the collectors of which are connected through resistors 108 and 110, respectively, to a positive potential source. The emitter of the transistor 100 is connected directly to ground, and the emitter of the transistor 102 is connected to ground through a reset switch 126. Although the reset switch 126 is illustrated as the push button type, other mechanical or electronic type switches may be employed. The base of the transistor 100 is connected to ground through a resistor 112, and the base of the transistor 102 is connected to ground through a resistor 114. The transistors are cross-coupled by a resistor 106 connected between the base of the transistor 100 and the collector of the 'transistor 102, and a resistor 104!- connected between the base of the transistor 102 and the collector of the transistor 100. Diodes 116 and 11S are connected at one end to the base electrode of the transistors 100 and 102, respectively, and at the other end to a coupling capacitor 120 which is connected to a trigger or complement input 11. A One output terminal 13 is connected to the junction of the resistors 1th; and 104 and a Zero output terminal 14 is connected to the junction of resistors 110 and 106. Each of the other flipflops 20, 30 and 40 includes the same circuit as that shown for the flip-flop 10. Each of the flip-flops is designed such thata positive potential at terminal 13 represents a One (transistor 10i) is nonconducting) and a positive potential at the terminal 14 represents a Zero (transistor 102 is nonconducting). to the trigger input terminal 11 causes the flip-flop to switch from one state to the other. It is to be understood that although a particular circuit is shown for the flip-flop 10, other transistorized bistable circuits may be employed as desired.

According to another feature of the invention, whenever the reset switch 126 is depressed 'the Zero transistor of each nip-flop is ungrounded. This action renders the Zero transistor nonconducting, and thus resets each of the dip-flops to the Zero state.

The inhibit gate 13 includes a diode 130, an input resistor 132 and a coupling capacitor 134 connected as shown. These components are arranged such that a bias from the flip-flop 1t) maybe applied to the cathode of the diode 130 through the resistor 132. When such a bias is applied to the gate 18, an input pulse applied to the anode of the diode 130 is blocked. Whenever the bias is removed the input pulse is passed by the diode 136, and this pulse is applied to the next succeeding stage through the coupling capacitor 134. The inhibit gates 28 and 38 are identical to the inhibit gate 18 and operate in the same manner. According to a further feature of this invention, this gating arrangement requires negligible current in the input of the gate and allows a high impedance (resistor 132) to be employed between the cathode of the diode and the output of the associated flip-flop. This high impedance prevents the counter from changing its accumulated total when the position of the add-subtract mode switch is changed. It is pointed out that other type inhibit gates may be employed without departing from the instant invention.

In the operation of the decade counter, ten of the sixteen possible binary states of the four hip-flops are used. At a decimal count of four in the add mode, and five in the subtract mode, the next pulse is fed to all four nipflops thereby complementing each of them. Input pulses cause the binary state of the counter to advance from 0 through 4 and then 11 through 15in the add mode. When the counter is operating in the subtract mode, the binary state decreases from through 11 and then 4 through 0. As will be apparent this scheme greatly reduces the total number of components that are required in the counter.

A positive input pulse applied Flip-Flops Decimal Counter Input ulses Value In the above Table I, a numeral 0 or a numeral 1 indicates that the ip-ilop is in the Zero or One state, respectively. It is assumed that all ofthe flip-flops are reset to Zero by the reset switch 126 which renders all of the right hand, or Zero, transistors nonconductive to thus reset all four flip-flops to Zero. Each of 'the inhibit gates 18, 28 and 33 is biased with a positive potential from the Zero terminals 12, 22 and 32, respectively, of the ipflops. The first input pulse is blocked by the inhibit gate 18 and the complement gate 60. An input pulse is passed by the complement gate 6G only when it is conditioned by the AND gate 59 as will be subsequently explained in greater detail. This rst input pulse, which is also applied to the trigger input 11 of the nip-flop 10, causes the ip-flop 10 to change from Zero to One as indicated in the above Table I. When the flip-flop 1t) changes its state from Zero to One, the positive bias applied to the inhibit gate 18 is removed. The second input pulse therefore may flow through the gate 18, but is blocked by the gate 28 which still has a positive bias applied thereto from the flip-flop 2t). This second pulse changes the state of each of the ip-flops 10 and 20. When the flip-flops 10 and 2h change state, a positive bias is reapplied to the inhibit gate 18 and removed from the inhibit gate 28. The third pulse is blocked by the inhibit gate 1S and, therefore, this pulse causes only the ip-op 10 to change state from Zero to One. The fourth input pulse finds the inhibit gates 18 and 28 unbiased and hence this pulse changes the states of the flip-flops 10, 20 and 30. As illustrated in Table I, after the fourth pulse the flip-flop 40 is in the Zero state, the flip-flop 3@ is in the One state, the flip-hop 2@ is in the Zero state and the flip-flop 10 is in the Zero state.

The fourth input pulse in the add mode conditions the counter so that the next input pulse, the tifth, complements the counter. After the fourth pulse the potential on each of the input terminals 52 and S of the ITI gate 5@ is the same, since the input terminal 52 is c011- nected to the Zero side of the flip-Hop 30 which is now at a zero potential, and the input terminal 54 is connected to the One side of the nip-flop 4@ which is at zero potential. ThisV coincidence of inputs to the T gate 50 produces an output from that gate which conditions the complement gate 60 to pass the next input pulse. This next input pulse (the fifth) complements the counter since it is applied directly to the ip-flop 10, applied to the flip-iops 2! and 30 through the diodes 70 and 80, respectively, and applied to the flip-lop 40 through the inhibit gate 38. Thus, it should be apparent from the above description and Table I that the fifth pulse, or the decimal number 5, is represented by a binary count of eleven in the counter. The subsequent sixth, seventh, eighth and ninth pulses each add one to 'the count in the counter. The numbers stored in the counter at any time may be read iout by sampling either of the output terminals of each of the ip-ops 10, 20, 30 and 40. For example, a neon indicator device may be connected from each of the One output terminals 13, 23, 33 and 43 to ground. With such an arrangement the neon devices light whenever their respective ip-ilops are in the One state.

The operation of the bidirectional decade counter of the present invention in the subtract mode is essentially the same as the operation in the add mode. To subtract, the mode switches 16, 26, 36 and 46 are each moved to their left-hand position, i.e., connected to terminals 13, 23, 33 and 42, respectively.

By reference to the drawing and to the following Table II, the operation of the counter in the subtract mode is as follows:

In the above Table II, a numeral or a numeral 1 indicates that the ip-iop is in the Zero or One state, respectively. It is assumed that all of the liip-ops are reset to Zero by the reset switch 126 which renders all of the right-hand transistors nonconductive to thus reset all four flip-flops to the Zero state.

The rst input pulse iinds each of the inhibit gates 18, 28 and 38 unbiased and, therefore, this pulse is applied to each of the liip-flops 10, 20, 30 and 40. This irst pulse thus causes each ofthe dip-flops to change state, and leaves each of the flip-flops in the One state. The second input pulse inds each of the inhibit gates 18, 23 and 38 biased since a positive potential is applied to each of these gates from the output terminals 13, 23 and 33, respectively. This second pulse causes only the flip-Hop 10 to change state. Each subsequent input pulse subtracts one from the count in the counter as illustrated in the above Table II. When the decimal value is established in the counter, the potentials applied to each of the input terminals S2 and 54 of the AND gate 50 from the flip-Hops 30 and 40, respectively, is the same. Upon the application of coincident inputs to the AND gate S0, this gate conditions the complement gate 60 to pass the next input pulse which complements the counter. This next input pulse is applied directly to the tiip-op 10, is applied to the fliplops 20 and Btl through the diodes 70 and 80, respectively, and is applied to the flip-flop 40 through the inhibit gate 38, thereby leaving a count of four in the counter. Subsequent input pulses continue to subtract one from the count in the counter.

It is seen that a transistorized bidirectional decade counter is provided by the present invention in which each input pulse increases the count by one in the add mode and decreases the count by one in the subtract mode. The counter employs a single set of gates and a switching arrangement to switch these gates from the Zero to the One side, or Vice versa, of certain of the flipiiops in the counter to control Whether the counter adds or subtracts. Another set of gates are used to complement the iiip-iiops after the occurrence of a particular count in the counter. The binary count represented by the counter increases from O through 4, then 11 through 15 when adding, and decreases from l5 through 11, then 4 through 0 when subtracting. This switching and counting arrangement greatly reduces the number of components required. The counter is reset by ungrounding one of the transistors of each flip-dop thereby resulting in a further reduction of components.

What is claimed is:

l. A bidirectional counter comprising: a plurality of stages each of which includes a bistable device having an input and at least one output; a plurality of gate means for gating pulses; lirst means connecting a iirst of said gate means to a rst of said bistable devices, a second of said bistable devices, and a second of said gate means; second means connecting said second gate means to said second bistable device, a succeeding bistable device and a succeeding gate means; third means connecting said succeeding gate means to said succeeding bistable device and a last of said bistable devices; a first gate; a second gate; means connecting said irst and second gates whereby the iirst gate is conditioned by the second gate; fourth means to apply pulses to said first bistable device, said iirst gate means and said rst gate; iifth means connecting said succeeding bistable device and said last bistable device to said second gate; and means connecting said irst gate to said second bistable device and to said succeeding bistable device; whereby certain of said bistable devices change state upon the application of input pulses by said fourth means.

2. A bidirectional counter as in claim 1 wherein each of said first, second, third and lifth" means includes a switch all of which are operated together to provide a count-up or a count-down operation of said counter.

3. A bidirectional counter as in claim l wherein each of said bistable devices includes a pair of transistors each of which is connected to ground; and said counter is reset by simultaneously removing the ground connection of one of said transistors of each of said bistable devices.

4. A bidirectional decade counter comprising: four stages each of which includes a bistable device having an input and two outputs, and three of said stages each includes a gate device; said gate devices being connected in series; a complement gate; an AND gate; a two-state switch means connected to one of the outputs on each of said bistable devices to connect the counter to count up or count down; means for receiving input pulses connected to a irst of said bistable devices, a irst of said gate devices and said complement gate; means connecting said gate devices to three of said bistable devices including said switch means whereby the states of the bistable devices condition the gate devices to pass or block said input pulses; the gate device of each stage being adapted to apply a pulse to the bistable device of the next succeeding stage; and said AND gate being connected to the switch means of the third and fourth bistable devices and to said complement gate to condition said complement gate to pass an input pulse when said third and fourth bistable devices are in predetermined states; whereby said counter counts up when said switch means is in a first of said two states and counts down when said switch means is in a second of said two states.

5. A counter comprising: a plurality of ilip-ops each of which includes a pair of transistors; iirst means to apply input pulses to the transistors of each of said ip-tiops including a plurality of gates each conditioned by said iiip-tlops to pass or block said input pulses; second means to complement certain of said flip-flops; a inode switch means connected between a first group of said iiip-iiops and said gates, and between a second group of said iiip-iiops and said second means to set the counter to count up or count down; whereby input pulses applied to the counter add to or subtract from the value in the counter depending upon the state of the mode switch, and each of the iiip-tlops of said counter is complemented by an input pulse when the ip-ops are in a predetermined state.

6. A counter as in claim 5 wherein each of said transistors is grounded and the counter is reset by ungrounding one transistor of each pair of transistors.

7. A counter as in claim 5 wherein said gates include a high impedance and said gates are connected through this impedance to said rst group of iiip-ops.

8. A bidirectional counter comprising: a plurality of transistor ip-ilops having at least a pair of output terminals; a set of gates; switch means connecting each of said gates to one or another of each of said output terminals on each of a group of said plurality of hip-flops to cause the counter to add or subtract, respectively; means applying pulses to the counter whereby the count in the counter increases or decreases; and gate means connecting another group of said plurality of iiip-ops to complement certain of the p-ops when all of the Hipops are in a predetermined state.

V9. A bidirectional counter as in claim 8 wherein the binary count in said counter increases from 0 through 4 and then 11 through 15 when adding; and decreases from 15 through 11 and then 4 through 0 when subtracting.

References Cited in the tile of this patent UNITED STATES PATENTS 2,816,226 Forrest et al. Dec. 10, 1957 2,841,705 Moerman July 1, 1958 2,931,922 Tubinis Apr. 5, 1960 2,977,539 Townsend Mar. 28, 1961 FOREIGN PATENTS 596,670 Great Britain Ian. 8, 1948 

8. A BIDIRECTIONAL COUNTER COMPRISING: A PLURALITY OF TRANSISTOR FLIP-FLOPS HAVING AT LEAST A PAIR OF OUTPUT TERMINALS; A SET OF GATES; SWITCH MEANS CONNECTING EACH OF SAID GATES TO ONE OR ANOTHER OF EACH OF SAID OUTPUT TERMINALS ON EACH OF A GROUP OF SAID PLURALITY OF FLIP-FLOPS TO CAUSE THE COUNTER TO ADD OR SUBTRACT, RESPECTIVELY; MEANS APPLYING PULSES TO THE COUNTER WHEREBY THE COUNT IN THE COUNTER INCREASES OR DECREASES; AND GATE MEANS CONNECTING ANOTHER GROUP OF SAID PLURALITY OF FLIP-FLOPS TO COMPLEMENT CERTAIN OF THE FLIP-FLOPS WHEN ALL OF THE FLIPFLOPS ARE IN A PREDETERMINED STATE. 